Scalability, power-efficiency and shorter time-to-market due to design re-use has paved the way for multi-core or many-core chips, wherein identical processing units (e.g., cores) are integrated together to offer enhanced computational power. (See, e.g., Reference 1). Chips with identical cores generally help cope with increasing defect rates in delivering reasonable yield levels via the utilization of spare cores. (See, e.g., References 2, 3, 4, 5, 6). With defective cores masked off, the remaining defect-free cores can still perform in compliance with the specifications of the chip. Binning of chips based on the number of defect-free cores has also been proposed. (See, e.g., References 2 and 5). The spare core approach can be advocated for not only enhancing yield, but also for alleviating test requirements, thus reducing test costs. (See, e.g., References 7 and 8).
The fact that the cores can be identical can be exploited to lower test costs. (See, e.g., Reference 9). In general, core-based or modular testing can benefit from the fact that a proper isolation mechanism can be in place. (See, e.g., References 10 and 11). With identical cores, the application of identical test patterns to each identical core can utilize a proper isolation mechanism that can deliver direct controllability/observability of core I/Os. Conventional Test Access Mechanisms (“TAMs”) (see, e.g., References 10 and 11) originally proposed to support heterogeneous cores, can be simplified to lower design and test costs in the presence of identical cores. Bandwidth and area consuming test busses can be replaced by simpler mechanisms, alleviating bandwidth and area costs. On the input side, this simplification can take the form of broadcasting the same test stimuli to the identical cores, lowering the input bandwidth requirements. Collection of responses from the identical cores must be carefully engineered, however, in order to cope with the unorthodox test challenges stemming from the presence of spare cores on-chip, which can invalidate the conventional single fault assumption. Failure to account for the spare cores in the TAM design can result in yield loss, offsetting the yield enhancement benefit of the spare core approach.
Direct extensions of conventional TAMs (see e.g., References 5, 6, 12 and 13) have been employed for chips with identical cores, failing to exploit core identicalness in attaining test cost reductions. These techniques can allocate dedicated scan-in and scan-out bandwidth to each core, and while the cores can be identical, the test is conducted as if the cores are non-identical. As previously known (see, e.g., Reference 3), the need to observe each identical core can be alleviated by loading the expected core responses from dedicated input channels, and comparing all the core responses with the expected responses in parallel. This approach can attain parallelism in identical core tests. However, bandwidth requirements for the outputs, although alleviated, can turn into additional input bandwidth requirements.
Comparison-based TAMs (see, e.g., References 14-16) have been proposed to eliminate the need for any bandwidth to be allocated for the responses of identical cores. The output responses of identical cores, stimulated by identical test patterns, can be compared on-chip, pair-wise, and any mismatch can be recorded in error bits. As previously known, a lock-step mode facilitates the broadcasting of the same patterns to two cores, and an on-chip comparator that can be continuously observed that can reveal any mismatch between identical cores. (See, e.g., Reference 14) Another approach can employ a test mode that enables similar comparisons, but also offers the option of observing an accumulated error signature rather than continuous observation of the comparator output. (See, e.g., Reference 15). A further approach can follow a similar approach by taking one core as a timing reference in testing the other identical core. (See, e.g., Reference 16). These comparison-based TAMs can incur yield loss for chips with spare cores as a good core compared with only defective core(s) can be deemed defective, albeit incorrectly.
Another approach that has recently been proposed can be a pipelined comparison-based TAM. (See, e.g., References 17 and 18). This TAM can support a self-compare mode, where the response of each core can be compared against the expected responses loaded from dedicated scan-inputs, or against the response of one core that can be taken as reference, which can be the inter-core compare mode. The bandwidth requirements of the former mode can be the same as previously described (see, e.g., Reference 3), while the latter mode can incur the same bandwidth requirement but for outputs rather than inputs. Furthermore, if the reference core can be identified to be defective in the latter mode, the test session can be repeated as the previous comparisons can all be invalidated. Further, the pipelining mechanism and the command control of these procedures can incur the allocation of four channels for control purposes, which can be shown to reflect into a 12% test time penalty. To alleviate the pipelining complications, previous approaches can make use of balancing registers at the inputs and outputs of each core, enabling simultaneous comparisons of core responses. However, multiple test sessions can be used. (See, e.g., Reference 19).
Comparison-based TAMs can perform poorly as a good core can be compared with only bad cores, even if these cores are known-bad cores. The mismatches obtained through all the comparisons can result in an ambiguous conclusion regarding the good core, as the end-result (e.g., always mismatches) could have been the same even if this good core can be defective.
FIG. 1 illustrates three exemplary scenarios, each for a chip with eight cores, two of which are spare cores. Six good cores out of eight cores can be considered as the passing criterion, and the test can be conducted by comparing each core with its two neighbors. As shown in FIG. 1, a node 105 can have a core 115 and an edge 110 can denote a comparison. The accumulated comparison signatures obtained throughout the test can be analyzed to judge whether the chip can be usable. A single bit signature collected for each comparison can indicate whether the response of two cores can perfectly match throughout the entire test. The actual defective cores 120 can be marked with an “X” inside the corresponding nodes.
In the first case 125, for example, four out of eight comparisons can indicate a perfect match between cores. The cores involved in these exemplary comparisons can thus be identified to be all “good”, pointing to the actual six good cores. The mismatches between the known-good cores and the remaining two cores can help conclude that these two cores are defective, non-ambiguously identifying all the good and the bad cores, and deeming the chip usable.
In the second case 130, for example, the four perfect matches can help exonerate five of the six good cores. These can be the three cores in the bottom row, and the two in the middle row. For example, the mismatches between the known-good cores and the cores in the top two corners can indicate that these two cores are both defective. The core between the top two corners, however, may not be identified as good or bad. The only information regarding this core can be the mismatches when compared to the two bad cores. As no other good core can witness for this core, one cannot tell whether it can be a good core or a bad core. Even though the chip can have six good cores, the comparison-based test can identify five good ones, failing to pass this usable chip, and resulting in yield loss.
The third case 135, can likely be the same as the second case, except that the core in between the top two corners can be defective. Again, all good cores are identified through four matches, and the cores on the top two corners can also be identified as defective through mismatches with the known-good cores. The core in between the top two corners can be questionable, again, as it can be compared with bad cores only. This chip fails the test, this time correctly.
The problem with the comparison-based TAMs can be the ambiguity regarding the cores that are compared with only bad cores, which can result in yield loss in the second case 130. Another way to understand this ambiguity can be by comparing the match-mismatch signatures of the last two cases. Both cases can result in the exact same eight-bit match/mismatch signatures, while the core in between the top two corners can be good in the second case 130, and defective in the third 135.
Other approaches can include (a) a two-dimensional pipelining approach that can utilize the first slice of each core as the pipelining registers (see, e.g., Reference 20), (b) application of the same test data repeatedly to identical cores through an embedded controller to reduce the test data volume but not the test time (see, e.g., Reference 21), (c) an on-line testing procedure that reaps test data storage and on-chip hardware support benefits due to identical cores (see, e.g., Reference 22), and (d) a failure diagnostics approach. (See, e.g., Reference 23). These exemplary TAMs can typically support a diagnostic mode where the fail data can be unloaded from the chip. The support can be in the form of either observing the responses of one particular core or of all cores. The latter approach can be inefficient in terms of diagnostic time, as known-good cores need not be observed. The former approach has to conduct a test session first to determine the failing core(s), which are then observed individually.
Thus, it may be beneficial to provide an exemplary system, method and computer-accessible medium that can that can reduce test bandwidth and test time, while preventing yield loss in the presence of spare cores, and which can overcome at least some of the deficiencies indicated herein above.